DC-Roma RISC-V AI PC preorder
https://deepcomputing.io/50-tops-dc-roma-risc-v-ai-pc-is-here/
https://redd.it/1knirdk
@r_riscv
https://deepcomputing.io/50-tops-dc-roma-risc-v-ai-pc-is-here/
https://redd.it/1knirdk
@r_riscv
DeepComputing
50 TOPS DC-ROMA RISC-V AI PC is Here! - DeepComputing
DeepComputing, in collaboration with Framework and powered by ESWIN Computing’s advanced RISC-V multi-purpose intelligent computing SoC EIC7702X—featuring 8 SiFive’s high-performance P550 CPU cores and pre-installed with Ubuntu Desktop 24.04 LTS— proudly…
Risc V starting point
I am a final year student of ECE and I wanna do some projects under risc v, I don't know where to start, what are the hardware and software requirements. Can anyone have any suggestions.
https://redd.it/1knvfde
@r_riscv
I am a final year student of ECE and I wanna do some projects under risc v, I don't know where to start, what are the hardware and software requirements. Can anyone have any suggestions.
https://redd.it/1knvfde
@r_riscv
Reddit
From the RISCV community on Reddit
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RISC-V Web IDE
Hello everyone!
During those years i've been developing a web IDE for assembly languages (asm-editor.specy.app), supporting M68K, MIPS, X86, and just today i finished adding RISC-V so i wanted to share it here!
It is made to teach people assembly, with many tools made to debug and make it easier to write assembly code (code completion, hover documentation, number conversions, stack tracing, undo history, step, breakpoints, undo, testcases etc...).
UI of the editor + debug tools
here is a sample fibonacci program
https://redd.it/1ko7efl
@r_riscv
Hello everyone!
During those years i've been developing a web IDE for assembly languages (asm-editor.specy.app), supporting M68K, MIPS, X86, and just today i finished adding RISC-V so i wanted to share it here!
It is made to teach people assembly, with many tools made to debug and make it easier to write assembly code (code completion, hover documentation, number conversions, stack tracing, undo history, step, breakpoints, undo, testcases etc...).
UI of the editor + debug tools
here is a sample fibonacci program
https://redd.it/1ko7efl
@r_riscv
asm-editor.specy.app
Asm Editor
Write, learn and run M68K, MIPS, X86 assembly code on your browser. View registers and memory, step and undo the program.
Sophgo RISC-V Compute Server SRA3-40
https://en.sophgo.com/sophon-u/product/introduce/sra3-40.html
https://redd.it/1kogsac
@r_riscv
https://en.sophgo.com/sophon-u/product/introduce/sra3-40.html
https://redd.it/1kogsac
@r_riscv
AEGIS: An Open Socketed ARMv9 Platform
https://hackaday.io/project/203123-aegis-an-open-socketed-armv9-platform
https://redd.it/1koj2nj
@r_riscv
https://hackaday.io/project/203123-aegis-an-open-socketed-armv9-platform
https://redd.it/1koj2nj
@r_riscv
hackaday.io
AEGIS: An Open Socketed ARMv9 Platform
What if ARM chips were socketed, open, and built for long-term ownership?
We’re building exactly that.
AEGIS is a new family of LGA-socketed ARMv9 processors and modular development boards designed for openness, repairability, and real-time system control.…
We’re building exactly that.
AEGIS is a new family of LGA-socketed ARMv9 processors and modular development boards designed for openness, repairability, and real-time system control.…
Machines build machines - AI creates a bootable VM (RISC-V!)
https://popovicu.com/posts/ai-creates-bootable-vm/
https://redd.it/1koye34
@r_riscv
https://popovicu.com/posts/ai-creates-bootable-vm/
https://redd.it/1koye34
@r_riscv
Popovicu
Machines build machines - AI creates a bootable VM
See how AI is pushing the boundaries of computer engineering. I'm sharing my journey driving AI to build a functional RISC-V 32-bit VM simulation, reaching the milestone of booting OpenSBI. Discover the process behind this AI-assisted journey and what's next…
Implementing a RISC-V Hypervisor
https://seiya.me/blog/riscv-hypervisor
https://redd.it/1kp5b48
@r_riscv
https://seiya.me/blog/riscv-hypervisor
https://redd.it/1kp5b48
@r_riscv
seiya.me
Implementing a RISC-V Hypervisor
Armv9 Architecture Helps Lift Arm To New Financial Heights
https://www.nextplatform.com/2025/05/12/armv9-architecture-helps-lift-arm-to-new-financial-heights/
https://redd.it/1kpcdzt
@r_riscv
https://www.nextplatform.com/2025/05/12/armv9-architecture-helps-lift-arm-to-new-financial-heights/
https://redd.it/1kpcdzt
@r_riscv
The Next Platform
Armv9 Architecture Helps Lift Arm To New Financial Heights
The Armv9 architecture has a lot of technical enhancements to commend it, but as far as Arm Holdings, the creator and licensor of the Arm architecture, is
From Berkeley Lab to Global Standard: RISC-V’s 15-Year Journey
https://www.sifive.com/blog/from-berkeley-lab-to-global-standard-risc-vs-15-ye
https://redd.it/1kpyu4x
@r_riscv
https://www.sifive.com/blog/from-berkeley-lab-to-global-standard-risc-vs-15-ye
https://redd.it/1kpyu4x
@r_riscv
SiFive
From Berkeley Lab to Global Standard: RISC-V’s 15-Year Journey
Looking for design and verification people for RISC-V vector unit development
Hi,
I am writing this on behalf of the small company called Chipfy, which is working on development of RISC-V vector unit, based on RVV1.0 spec and aimed for HPC market.
We are looking for talented people with CPU design/verification/architecture background who want to join our team ( currently it is 10 people and growing ).
For all details please send me DM.
https://redd.it/1kq640r
@r_riscv
Hi,
I am writing this on behalf of the small company called Chipfy, which is working on development of RISC-V vector unit, based on RVV1.0 spec and aimed for HPC market.
We are looking for talented people with CPU design/verification/architecture background who want to join our team ( currently it is 10 people and growing ).
For all details please send me DM.
https://redd.it/1kq640r
@r_riscv
Reddit
From the RISCV community on Reddit
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RISC-V P-Extenstion implementation on FPGA
Hey everyone!
Me and my team are trying to implement the RISC-V P-Extension (Packed SIMD) on FPGA, but honestly, we have no idea where to start.
Can someone please guide us on:
How to approach the implementation on FPGA? Any good resources or tutorials?
Which toolchains or simulators support the RISC-V P-Extension?
Best practices for adding SIMD instructions to a base RISC-V core on FPGA?
Any open-source projects or examples we can check out?
We want to understand the full workflow—from modifying the core, simulating it, synthesizing, to testing on hardware.
Thanks a lot in advance for any help!
https://redd.it/1kqbep4
@r_riscv
Hey everyone!
Me and my team are trying to implement the RISC-V P-Extension (Packed SIMD) on FPGA, but honestly, we have no idea where to start.
Can someone please guide us on:
How to approach the implementation on FPGA? Any good resources or tutorials?
Which toolchains or simulators support the RISC-V P-Extension?
Best practices for adding SIMD instructions to a base RISC-V core on FPGA?
Any open-source projects or examples we can check out?
We want to understand the full workflow—from modifying the core, simulating it, synthesizing, to testing on hardware.
Thanks a lot in advance for any help!
https://redd.it/1kqbep4
@r_riscv
Reddit
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stval CSR content when interrupt no.13 is received
Official documentation says it should currently be zero. So how would a supervisor react to that interrupt? It seems a pretty useless trap when no further details are provided by the hardware, like the 12bit index of the "offending" CSR. Any hint?
https://redd.it/1kqe5ye
@r_riscv
Official documentation says it should currently be zero. So how would a supervisor react to that interrupt? It seems a pretty useless trap when no further details are provided by the hardware, like the 12bit index of the "offending" CSR. Any hint?
https://redd.it/1kqe5ye
@r_riscv
riscv.github.io
The RISC-V Instruction Set Manual: Volume II: Privileged Architecture
Volume II - Privileged Architecture
FOSDEM 2025 - Upstream Embedded Linux on RISC-V: The Good, the Bad and the Ugly [video, spacemit]
https://fosdem.org/2025/schedule/event/fosdem-2025-6342-upstream-embedded-linux-on-risc-v-the-good-the-bad-and-the-ugly/
https://redd.it/1kqoei2
@r_riscv
https://fosdem.org/2025/schedule/event/fosdem-2025-6342-upstream-embedded-linux-on-risc-v-the-good-the-bad-and-the-ugly/
https://redd.it/1kqoei2
@r_riscv
fosdem.org
FOSDEM 2025 - Upstream Embedded Linux on RISC-V: The Good, the Bad and the Ugly
Running AI-Enabled Ubuntu on HiFive Premier P550^^
Three months ago, I installed an AI-enabled Debian image on the P550 board, and the experience was quite good (you can check out my previous post here: [Running AI-enabled Debian on HiFive Premier P550](https://www.reddit.com/r/RISCV/comments/1ilul5c/runningaienableddebianonhifivepremierp550/)). However, I still prefer working with Ubuntu, which did not have AI capabilities enabled at that time. A couple of days ago, I discovered that ESWIN had updated an AI-enabled Ubuntu image. I proceeded to install and test it. This new image supports NPU and video hardware codec functionalities and includes support for DeepSeek 7B. In terms of features and performance, there is not much difference compared to the Debian image. But finally, I can now experience AI capabilities on Ubuntu, which is good news for me.\^\\^
If anyone is interested, you can also install and try it out. Here is the download link for the AI-enabled Ubuntu image: https://github.com/guopf307/risc-v-gadget/tree/ubuntu-p550.
https://redd.it/1kqte4d
@r_riscv
Three months ago, I installed an AI-enabled Debian image on the P550 board, and the experience was quite good (you can check out my previous post here: [Running AI-enabled Debian on HiFive Premier P550](https://www.reddit.com/r/RISCV/comments/1ilul5c/runningaienableddebianonhifivepremierp550/)). However, I still prefer working with Ubuntu, which did not have AI capabilities enabled at that time. A couple of days ago, I discovered that ESWIN had updated an AI-enabled Ubuntu image. I proceeded to install and test it. This new image supports NPU and video hardware codec functionalities and includes support for DeepSeek 7B. In terms of features and performance, there is not much difference compared to the Debian image. But finally, I can now experience AI capabilities on Ubuntu, which is good news for me.\^\\^
If anyone is interested, you can also install and try it out. Here is the download link for the AI-enabled Ubuntu image: https://github.com/guopf307/risc-v-gadget/tree/ubuntu-p550.
https://redd.it/1kqte4d
@r_riscv
Reddit
From the RISCV community on Reddit: Running AI-Enabled Debian on HiFive Premier P550
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Can't step through code in VS Code + OpenOCD + GDB with RISC-V — everything connects but stepping doesn't work
Hi! I'm setting up debugging for a RISC-V project in VS Code using the Cortex-Debug extension. I'm using OpenOCD and `riscv32-unknown-elf-gdb`. The configuration seems to launch correctly: OpenOCD starts, GDB connects, and the ELF file (`main.elf`) is loaded. A breakpoint in `main()` also sets successfully.
But then I run into problems:
* After `exec-continue`, the program stops at `0x00010058 in ?? ()`.
* The breakpoint in `main()` doesn’t hit, and I can’t step through the code (step over / step into doesn’t work).
* `main()` is at `0x400000c0`, and the ELF is built with `-g`, but something is clearly off.
# What I’ve checked:
* `"showDevDebugOutput": "parsed"` is set
* The ELF file contains debug symbols (verified with `nm`, `objdump`)
* Using custom `riscv.cfg` and my own `startup.S`
* Using `riscv32-unknown-elf-gdb` and OpenOCD listening on `localhost:50000`
* `readelf` shows the entry point does **not** match the address of `main()`
launch.json
{
"configurations": [
{
"name": "RISCV",
"type": "cortex-debug",
"request": "launch",
// "showDevDebugOutput": "parsed",
"servertype": "openocd",
"cwd": "${workspaceFolder}",
"executable": "./build/main.elf",
"gdbTarget": "localhost:50000",
"configFiles": [
"lib/riscv.cfg"
],
"postLaunchCommands": [
"load"
],
"runToEntryPoint": "main"
}
]
}
settings.json
{
"cortex-debug.openocdPath": "/usr/bin/openocd",
"cortex-debug.variableUseNaturalFormat": true,
"cortex-debug.gdbPath": "/home/riscv/bin/riscv32-unknown-elf-gdb",
"search.exclude": {
"**/build": true
},
"files.associations": {
"printf_uart.h": "c"
}
}
https://redd.it/1kr1rao
@r_riscv
Hi! I'm setting up debugging for a RISC-V project in VS Code using the Cortex-Debug extension. I'm using OpenOCD and `riscv32-unknown-elf-gdb`. The configuration seems to launch correctly: OpenOCD starts, GDB connects, and the ELF file (`main.elf`) is loaded. A breakpoint in `main()` also sets successfully.
But then I run into problems:
* After `exec-continue`, the program stops at `0x00010058 in ?? ()`.
* The breakpoint in `main()` doesn’t hit, and I can’t step through the code (step over / step into doesn’t work).
* `main()` is at `0x400000c0`, and the ELF is built with `-g`, but something is clearly off.
# What I’ve checked:
* `"showDevDebugOutput": "parsed"` is set
* The ELF file contains debug symbols (verified with `nm`, `objdump`)
* Using custom `riscv.cfg` and my own `startup.S`
* Using `riscv32-unknown-elf-gdb` and OpenOCD listening on `localhost:50000`
* `readelf` shows the entry point does **not** match the address of `main()`
launch.json
{
"configurations": [
{
"name": "RISCV",
"type": "cortex-debug",
"request": "launch",
// "showDevDebugOutput": "parsed",
"servertype": "openocd",
"cwd": "${workspaceFolder}",
"executable": "./build/main.elf",
"gdbTarget": "localhost:50000",
"configFiles": [
"lib/riscv.cfg"
],
"postLaunchCommands": [
"load"
],
"runToEntryPoint": "main"
}
]
}
settings.json
{
"cortex-debug.openocdPath": "/usr/bin/openocd",
"cortex-debug.variableUseNaturalFormat": true,
"cortex-debug.gdbPath": "/home/riscv/bin/riscv32-unknown-elf-gdb",
"search.exclude": {
"**/build": true
},
"files.associations": {
"printf_uart.h": "c"
}
}
https://redd.it/1kr1rao
@r_riscv
Reddit
From the RISCV community on Reddit
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Hosted RISC-V Runners for CI/CD runtimes
https://www.riscvrunners.com/
https://redd.it/1kr5o5l
@r_riscv
https://www.riscvrunners.com/
https://redd.it/1kr5o5l
@r_riscv
Red Hat Enterprise Linux 10.0 Formally Announced, Joined By RISC-V Developer Preview
https://www.phoronix.com/news/Red-Hat-Enterprise-Linux-10.0
https://redd.it/1krcqrm
@r_riscv
https://www.phoronix.com/news/Red-Hat-Enterprise-Linux-10.0
https://redd.it/1krcqrm
@r_riscv
Phoronix
Red Hat Enterprise Linux 10.0 Formally Announced, Joined By RISC-V Developer Preview
While Red Hat Enterprise Linux 10.0 GA images have been available for download since last week, Red Hat used the Red Hat Summit this week in Boston to formally announce the Red Hat Enterprise Linux 10 availability.
SuperTuxKart official package
I'm planning to build official RISC-V package for upcoming 1.5 release and I'm looking for someone who can actually test if it works. I have only old visionfive board without GPU, so it's unplayable there.
https://github.com/supertuxkart/stk-code/releases/download/preview/SuperTuxKart-git20250521-linux-riscv64.tar.gz
It's built on Debian Trixie, so glibc 2.41 is needed. And it uses OpenGL ES for rendering.
https://redd.it/1ksjg8a
@r_riscv
I'm planning to build official RISC-V package for upcoming 1.5 release and I'm looking for someone who can actually test if it works. I have only old visionfive board without GPU, so it's unplayable there.
https://github.com/supertuxkart/stk-code/releases/download/preview/SuperTuxKart-git20250521-linux-riscv64.tar.gz
It's built on Debian Trixie, so glibc 2.41 is needed. And it uses OpenGL ES for rendering.
https://redd.it/1ksjg8a
@r_riscv
Reddit
From the RISCV community on Reddit
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Facing problem interfacing SG90 Servo with CH32V0003F4U6.
When I use hs-485 servo with my code it works .but when I switch to micro servo sg90 it doesn't respond. Does anyone know how to solve this. I'm providing 5v from a adapter and it shares common ground and all.
https://redd.it/1kskze0
@r_riscv
When I use hs-485 servo with my code it works .but when I switch to micro servo sg90 it doesn't respond. Does anyone know how to solve this. I'm providing 5v from a adapter and it shares common ground and all.
https://redd.it/1kskze0
@r_riscv
Reddit
From the RISCV community on Reddit
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Semidynamics' Latest Cervell™ All-in-One IP Redefines Heterogeneous Compute With RISC-V
https://www.youtube.com/watch?v=OwiARaGtw48
https://redd.it/1ksxq1d
@r_riscv
https://www.youtube.com/watch?v=OwiARaGtw48
https://redd.it/1ksxq1d
@r_riscv
YouTube
Semidynamics' Latest Cervell™ All-in-One IP Redefines Heterogeneous Compute With RISC-V
Volker H. Politz, Chief Sales Officer at Semidynamics, explains why the company's Cervell™ All-in-One IP is so much more than an NPU — combining a CPU, Tensor unit, Vector unit, and Gazillion Misses memory controller in one IP core.